1. Field of the Invention
The present invention relates to a semiconductor device built-in multilayer wiring board and a method of manufacturing such a wiring board, and relates particularly to a semiconductor device built-in multilayer wiring board suitable for use in a high density, ultra small three dimensional mounting module formed by laminating a plurality of wiring substrates comprising a semiconductor device mounted on a wiring substrate, and to a method of manufacturing such a wiring board.
2. Description of Related Art
In recent years, by mounting not only passive components such as resistors and capacitors, but also small active components such as micro semiconductor packages, semiconductor bare chips and FBGA (fine pitch ball grid array), onto substrates such as printed laminates and ceramic laminates, the packaging density of components on the substrate has been increased, and surface mounting methods have been used to achieve improved miniaturization, and reductions in the weight and thickness of electronic devices. This type of surface mounting method seeks to reduce the size of each individual component.
Furthermore, in order to further improve the packaging density, three dimensional mounting modules are being developed, which employ three dimensional mounting technology to stack semiconductor devices in a three dimensional manner. In these three dimensional mounting modules, components which cannot be positioned via the surface mounting methods described above, especially large semiconductor devices, are either positioned vertically above the other components, or are embedded within the substrate, thereby enabling the packaging density to be increased.
The three dimensional mounting technology described above has recently become the focus of much attention, not only as a method of miniaturizing equipment, but also as a technology capable of contributing to increases in the speed of computers and communication equipment and the like.
For example, it is envisaged that video communication functions using an image capture element, Bluetooth interface functions and GPS functions and the like will be incorporated within communication devices, and the increase in the number of components accompanying this move towards greater functionality is creating a significant need for higher density packaging technology. In particular, if a number of semiconductor chips, which represent small semiconductor devices, are laminated and wired together in a three dimensional manner, then the length of wiring can be reduced, enabling the transmission of high speed signals, and as a result the adoption of three dimensional mounting technology is essential for future applications.
Three dimensional mounting technology can be broadly classified into two types. One type relates to three dimensional mounting modules in which components are laminated internally or onto a printed wiring board, and the other type relates to three dimensional mounting packages in which semiconductor chips are laminated together inside a package.
The former technology has gained very little popularity as it requires the equipment makers using such three dimensional mounting modules to undertake significant research and development of specialized mounting devices. In contrast, in the case of the latter technology, the electronic makers manufacturing such three dimensional mounting packages are seeking to differentiate themselves from other makers on the basis of the variety and number of semiconductor chips, and the number of laminated wiring boards within a package, or in the case of a similar package, on the basis of the variety of functions exhibited by the package, and consequently the LSI makers are beginning to commit significant resources to development of these packages.
One example of a three dimensional mounting package capable of laminating a plurality of semiconductor chips within a single package regardless of the type or shape of the chips is the System Block Module (SBM) developed by Toshiba Corporation (for example, refer to “Sanjigen mojuru no tenbo” (The outlook for three dimensional modules), by Morihiko Ikemizu, in Erekutoronikusu jisso gijutsu (Electronics Packaging Technologies), Gicho Publishing and Advertising Co., Ltd., April 2000, Vol. 16, No. 4, p. 32 to 34). This SBM uses a configuration in which semiconductor chips which have been reduced down to a thickness of 50 μm are mounted onto a heat resistant resin wiring board formed from a glass epoxy resin or the like, and a plurality of these wiring boards are then laminated together. With this type of SBM, the thickness of a single layer is approximately 140 μm, and consequently 7 chip layers can be laminated within a single package of thickness 1 mm. Furthermore, the wiring pattern between terminals is formed on those sections of the boards on which semiconductor chips are not mounted, and the chip terminals and the boards are connected electrically directly via Au bumps, whereas the electrical connections between semiconductor chips is achieved via wiring formed from a conductive material embedded within holes formed in boards sandwiched between each set of layers.
However, in conventional three dimensional mounting packages, because semiconductor chips are typically mounted on heat resistant resin wiring boards formed from a glass epoxy or the like, the shape and packaging density of the package are restricted by existing board materials and board processes, and consequently increases in the packaging density and further miniaturization are difficult to achieve beyond these restrictions.
For example, although heat resistant resins such as a glass epoxy resin offer advantages as highly heat resistant substrate materials, when the heat resistant resin is laminated and integrated into a single unit, the heat resistant resin must first be converted to a semi cured state, and this semi cured heat resistant resin must then be heated to enable thermal fusion, and a problem arises during this heating and thermal fusion in that a resin flow, resulting from a large reduction in the modulus of elasticity, may cause distortions in the conducting material which forms the wiring circuit.
In addition, conventional three dimensional mounting package production lines are suited to high volume low mix production, and consequently there is tendency for the production facilities to increase in size. Furthermore, wet processes such as chemical etching (wet etching) and plating techniques are typically used during the formation of wiring circuits on the glass epoxy heat resistant resin substrates, and these techniques are undesirable from the viewpoint of environmental impact.
Examples of alternative methods to these wet processes include dry processes such as screen printing methods and dispensing methods using a conductive paste, although in both of these methods, there is a limit to the improvements in detail and precision of the conductive wiring which can be achieved in order to try and meet the ever increasing demands for higher density packaging.
In addition, in a three dimensional mounting package using a conductive paste, the heat resistant resin must be heated to a temperature close to the melting point and subjected to pressure in order to fuse the heat resistant resin layers together and create a single integrated unit, and as the pitch of the wiring becomes finer, distortion of the wiring resulting from resin flow during lamination is increasingly becoming a factor which cannot be ignored in substrate design.